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respectively). This master clock input is then provided to the CODEC and the XS1

device.

3.8.1 Port Conﬁguration (CODEC Slave)

The default software conﬁguration is CODEC Slave (XS1 master). That is, the XS1

provides the BCLK and LRCLK signals to the CODEC.

XS1 ports and XS1 clocks provide many valuable features for implementing I2S.

This section describes how these are conﬁgured and used to drive the I2S interface.

L8A-64-TQ128

p_mclk

p_sdin

clk_audio_mclk

clk_audio_bclk

Audio master clock

CODEC

p_bclk

p_lrclk

p_sdout

Figure 12:

Ports and

Clocks

(CODEC slave)

The code to conﬁgure the ports and clocks is in the

ConfigAudioPorts()

function.

Developers should not need to modify this.

The L-Series device inputs MCLK and divides it down to generate BCLK and LRCLK.

To achieve this, MCLK is input into the device using the 1-bit port

p_mclk

. This

is attached to the clock block

clk_audio_mclk

, which is in turn used to clock the

BCLK port,

p_bclk

. BCLK is used to clock the LRCLK (

p_lrclk

) and data signals

SDIN (

p_sdin

) and SDOUT (

p_sdout

). Again, a clock block is used (

clk_audio_bclk

)

which has

p_bclk

as its input and is used to clock the ports

p_lrclk

p_sdin

and

p_sdout

. The preceding diagram shows the connectivity of ports and clock blocks.

p_sdin

and

p_sdout

are conﬁgured as buﬀered ports with a transfer width of 32,

so all 32 bits are input in one input statement. This allows the software to input,

process and output 32-bit words, whilst the ports serialize and deserialize to the

single I/O pin connected to each port.

Buﬀered ports with a transfer width of 32 are also used for

p_bclk

and

p_lrclk

The bit clock is generated by performing outputs of a particular pattern to

p_bclk

to toggle the output at the desired rate. The pattern depends on the divide between

MCLK and BCLK. The following table shows the pattern for diﬀerent values of this

divide:

REV 6.1

1 2 ... 15 16 17 18 19 20 21 22 23 24 25 ... 61 62

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